1. Technical Field
Some embodiments of the present invention generally relate to memory technologies. In particular, certain embodiments relate to the activation of partial pages in memory.
2. Discussion
The popularity of computing systems continues to grow and the demand for more computing functionality has reached new heights. With this demand has come a number of concerns regarding memory structures. For example, although the development of double data rate (e.g., DDR Synchronous Dynamic Random Access Memory/SDRAM Specification, JESD79D, JEDEC Solid State Technology Association, January 2004; DDR2 SDRAM Specification, JESD79-2A, JEDEC Solid State Technology Association, January 2004, etc.) memory technologies has increased the rate at which data can be written to and read from DRAM, difficulties with power consumption often remain.
In particular, activating a bank of memory can be a power intensive operation due to page size. Page size typically refers to the minimum number of column locations that are on any row and are accessed with a single ACTIVATE command, where each time an ACTIVATE command is issued, all the bits within the page are often read by an array of sense amplifiers and restored to their correct value. In a DRAM, to meet various system requirements across desktop, mobile and server systems, DDR technologists have adopted a standard page size definition. For example for a 512 Mb x16 device configuration, the page size has been defined as 2 KB. When a memory controller activates a bank by supplying a row address (A0-A12 for the 512 Mb DRAM example), a row equivalent to a page size of 2 KB can be loaded into the sense amp array. This 2 KB page size equates to 16,384 bits. Out of these bits only 16 bits are typically transferred out at each clock edge. Due to the burst mode nature of DDR technology, 128 bits could therefore be accessed in 4 clocks. Accordingly, this scheme of activating all 16,384 bits may not be well suited for applications that are not fetching a complete 2 KB from (or writing a complete 2 KB to) each DRAM device. Thus, for certain applications, activating a full page size could be a wasteful activity.